View HT45R38_1137360.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HT45R38 C/R to F Type 8-Bit OTP MCU
Technical Document
* Tools Information * FAQs * Application Note
Features
* Operating voltage: * 12 capacitor/resistor sensor input * 409615 program memory * 1928 data memory RAM * Power Down and Wake-up function reduce power
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
* 29 bidirectional I/O lines * Two external interrupt inputs shared with I/O lines * Single 8-bit programmable timer/event counter with
consumption
* Up to 0.5ms instruction cycle with 8MHz system clock
overflow interrupt and 7-stage prescaler
* One 8-bit programmable timer/event counter with
at VDD=5V
* All instructions executed in one or two machine cy-
overflow interrupt
* 5 channels 12-bit resolution A/D converter * 2-channels 8-bit PWM output shared with 2 I/O lines * One OPA * External RC oscillation converter * On-chip crystal and RC oscillator * Watchdog Timer
cles
* 15-bit table read instruction * Six-level subroutine nesting * Bit manipulation instruction * 63 powerful instructions * Low voltage reset function * 52-pin QFP package
General Description
The HT45R38 is an 8-bit high performance, RISC architecture microcontroller device specifically designed for cost-effective multiple I/O control product applications. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, Power Down and wake-up functions, Watchdog Timer, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem controllers, etc.
Rev. 1.00
1
December 13, 2006
HT45R38
Block Diagram
P A 3 /IN T 0 P A 4 /IN T 1 In te rru p t C ir c u it IN T C
STACK0 P ro g ra m ROM P ro g ra m C o u n te r STACK1
TM R0C TM R0 M U X P r e s c a le r P A 5 /T M R 0
S y s te m
C lo c k
TM R1C In s tr u c tio n R e g is te r MP M U X D a ta M e m o ry TM R1 M U X
S y s te m
C lo c k /4
P A 6 /T M R 1
W DTS W D T P r e s c a le r
In s tr u c tio n D ecoder ALU T im in g G e n e ra to r S h ifte r MUX
WDT
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 /P W /P W /IN /IN /T /T
M U
S y s te m X
M0 M1 T0 RC OSC
C lo c k /4
PW M
S ta tu s PAC PA PORT A
T1 MR0 MR1
PBC PB
OSC2 OS RE VD VD VS VS S S D C1 DB SC ACC
PORT B
PB0~PB7
PCC PC
PORT C
PC 0~PC 7
5 -C h a n n e l A /D C o n v e rte r PEC PE T im e r A
M U X
PORT E
P E 0 /A N 0 /O P O P E 1 /A N 1 ~ P E 4 /A N 4 S y s te m S y s te m C lo c k C lo c k /4
T im e r B A n a lo g S w itc h RC O s c illa tio n
R C O s c illa tio n O u tp u t R C 1~R C 12 RCOUT
IN RREF CREF P E 0 /A N 0 /O P O OPN OPP
Rev. 1.00
2
December 13, 2006
HT45R38
Pin Assignment
P E 0 /A N 0 /O O O V V OS OS R P A 0 /P W P A 1 /P W P P A 3 /IN P A 4 /IN PO PN PP SS DD C2 C1 ES M0 M1 A2 T0 T1
52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35
P A 5 /T M R P A 6 /T M R PA PB PB PB PB VDD PB PB PB PB PC B
3 5 6 7 0 4
2
1
0
7
1
0
H T45R 38 5 2 Q F P -A
34 33 32 31 30 29 28 27
PE PE PE PE RC RC RC RC RC RC RC RC RC
1 /A 2 /A 3 /A 4 /A 12 11 10 9 8 7 6 5 4
N1 N2 N3 N4
RC3 RC2 RC1 RCO IN RRE CRE PC5 PC4 VSS PC3 PC2 PC1 C F UT F
Pin Description
Pin Name PA0/PWM0 PA1/PWM1 PA2 PA3/INT0 PA4/INT1 PA5/TMR0 PA6/TMR1 PA7 I/O Options Description Bidirectional 8-bit I/O port. Each pin can be configured as a wake-up input by configuration code options. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Pull-high resistors can be connected to each pin via configuration options. Pins PA3 and PA4 are pin-shared with external interrupt input pins INT0 and INT1, respectively. Configuration options determine the interrupt enable/disable and the interrupt low/high trigger type. Pins PA5 and PA6 are pin-shared with the external timer input pins TMR0 and TMR1. The PWM0/PWM1 output functions are pin-shared with PA0/PA1, respectively. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Pull-high resistors can be added to the whole port via a configuration option. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Pull-high resistors can be added to the whole port via a configuration option. OPN is the OPA inverting input pin OPP is the OPA non-inverting input pin Bidirectional 5-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Pull-high resistors can be connected to each pin via configuration options. PE0~PE4 are pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor are disabled automatically. The OPO is the OPA output pin and pin-shared with PE0/AN0. Capacitor or resistor connection pins Capacitor or resistor connection pin to RC OSC Oscillation input pin Reference resistor connection pin Reference capacitor connection pin Schmitt trigger reset input. Active low
I/O
Pull-high Wake-up Interrupt Enable Interrupt Active Edge Type PWM
PB0~PB7
I/O
Pull-high
PC0~PC7 OPN OPP
I/O
Pull-high
I
3/4
PE0/AN0/OPO PE1/AN1 I/O PE2/AN2 PE3/AN3 PE4/AN4 RC1~RC12 RCOUT IN RREF CREF RES I I I O O I
Pull-high
3/4 3/4 3/4 3/4 3/4 3/4
Rev. 1.00
3
December 13, 2006
HT45R38
Pin Name VSS VSSC VDD VDDB OSC1 OSC2 I/O 3/4 3/4 3/4 3/4 I O Options 3/4 3/4 3/4 3/4 Description Negative power supply, ground Negative power supply for PC, ground Positive power supply Positive power supply PB OSC1, OSC2 are connected to an RC network or Crystal determined by a configuration option, for the internal system clock. In the case of the RC oscillator, OSC2 can be used to monitor the system clock. Its frequency is 1/4 system clock.
Crystal or RC
Note: *All pull-high resistors are controlled by an option bit.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................300mA Total Power Dissipation .....................................500mW Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-200mA
D.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 3V 5V 5V 3V Standby Current (WDT Enabled) 5V ISTB2 VIL1 VIH1 VIL2 VIH2 VLVR IOL1 3V Standby Current (WDT Disabled) 5V Input Low Voltage for I/O Ports, TMR0, TMR1, INT0 and INT1 Input High Voltage for I/O Ports, TMR0, TMR1, INT0 and INT1 Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset PA, PB, PE, RREF and CREF Sink Current PA, PC, PE, RREF and CREF Source Current 3/4 3/4 3/4 3/4 3/4 3V 5V 3V 5V VOH=0.9VDD 3/4 3/4 3/4 3/4 LVR enabled VOL=0.1VDD No load, system HALT No load, system HALT No load, fSYS=8MHz Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=4MHz Min. 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 2.7 4 10 -2 -5 Typ. 3/4 3/4 1 3 4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3.0 8 20 -4 -10 Max. 5.5 5.5 2 5 8 5 10 1 2 0.3VDD VDD 0.4VDD VDD 3.3 3/4 3/4 3/4 3/4
Ta=25C Unit V V mA mA mA mA mA mA mA V V V V V mA mA mA mA
VDD
Operating Voltage Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC)
IDD1 IDD2 ISTB1
IOH1
Rev. 1.00
4
December 13, 2006
HT45R38
Symbol Parameter Test Conditions VDD 3V PC Sink Current 5V IOH2 3V PB Source Current 5V RPH VAD DNL INL 3V Pull-high Resistance 5V A/D Input Voltage ADC Differential Non-Linear ADC Integral Non-Linear 3/4 3/4 3/4 3/4 3/4 3/4 ADC input reference voltage is VDD 3/4 3/4 3/4 3/4 3/4 VOH=0.9VDD Conditions VOL=0.1VDD Min. 8 20 -4 -10 20 10 0 3/4 3/4 3/4 3/4 3/4 Typ. 16 40 -8 -20 60 30 3/4 3/4 2.5 3/4 0.5 1.5 Max. 3/4 3/4 3/4 3/4 100 50 VDD 2 4 12 1 3 Unit mA mA mA mA kW kW V LSB LSB Bits mA mA
IOL2
RESOLU Resolution IADC
Additional Power Consumption if A/D 3V Converter is Used 5V
A.C. Characteristics
Symbol Parameter System Clock (Crystal OSC, RC OSC) Timer I/P Frequency Test Conditions VDD 3/4 3/4 3/4 3/4 3V 5V tWDT1 tWDT2 tRES tSST tINT tLVR tAD tADC tADCS Watchdog Time-out Period (WDT RC OSC) Watchdog Time-out Period (System Clock/4) External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width Low Voltage Reset Time A/D Clock Period A/D Conversion Time A/D Sampling Time 3V 5V 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 3/4 Without WDT prescaler Without WDT prescaler 3/4 Wake-up from HALT 3/4 3/4 3/4 3/4 3/4 Min. 400 400 0 0 45 32 11 8 3/4 1 3/4 1 0.25 1 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 90 65 23 17 1024 3/4 1024 3/4 1 3/4 80 32 Max. 4000 8000 4000 8000 180 130 46 33 3/4 3/4 3/4 3/4 2 3/4 3/4 3/4
Ta=25C Unit kHz kHz kHz kHz ms ms ms ms tSYS ms tSYS ms ms ms tAD tAD
fSYS
fTIMER
tWDTOSC Watchdog Oscillator Period
Rev. 1.00
5
December 13, 2006
HT45R38
OP Amplifier Electrical Characteristics
Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Ta=25C Unit
D.C. Electrical Characteristic VDD VOS VCM PSRR CMRR Operating Voltage Input Offset Voltage Common Mode Voltage Range Power Supply Rejection Ratio Common Mode Rejection Ratio 3/4 5V 3/4 3/4 3/4 3/4 By calibration 3/4 3/4 VDD=5V VCM=0~VDD-1.4V 3/4 No load RL=1MW, CL=100pF 3 -2 VSS 60 60 3/4 3/4 3/4 3/4 3/4 5.5 +2 VDD-1.4 3/4 3/4 V mV V dB dB
D.C. Electrical Characteristic AOL SR GBW Open Loop Gain Slew Rate+, RateGain Band Width 3/4 3/4 3/4 60 3/4 3/4 80 1 3/4 3/4 3/4 100 dB V/ms kHz
Rev. 1.00
6
December 13, 2006
HT45R38
Functional Description
Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in program ROM are executed and its contents specify full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m O S C 2 (R C C lo c k o n ly ) PC PC PC+1 PC+2 T1 T2 T3 T4 T1
incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, a conditional skip execution, loading the PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt or return from a subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise the program will proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writable register (06H). Moving data into the PCL performs a short jump. The destination must be within the current Program Memory Page. When a control transfer takes place, an additional dummy cycle is required.
T2 T3 T4 T1 T2 T3 T4
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *11 0 0 0 0 0 0 0 *11 *10 0 0 0 0 0 0 0 *10 *9 0 0 0 0 0 0 0 *9 #9 S9 *8 0 0 0 0 0 0 0 *8 #8 S8 *7 0 0 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 0 0 @6 #6 S6 *5 0 0 0 0 0 0 0 @5 #5 S5 *4 0 0 0 0 1 1 1 @4 #4 S4 *3 0 0 1 1 0 0 1 @3 #3 S3 *2 0 1 0 1 0 1 0 @2 #2 S2 *1 0 0 0 0 0 0 0 @1 #1 S1 *0 0 0 0 0 0 0 0 @0 #0 S0
Mode Initial Reset External Interrupt 0 External Interrupt 1 Timer/Event Counter 0 Overflow External RC Oscillation Converter Interrupt Timer/Event Counter 1 Overflow A/D Converter Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter+2 #11 #10 S11 S10
Program Counter Note: *11~*0: Program Counter bits #11~#0: Instruction code bits Rev. 1.00 7 S11~S0: Stack register bits @7~@0: PCL bits December 13, 2006
HT45R38
Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 409615 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H * Location 00CH
This location is reserved for the Timer/Event Counter 0 interrupt service program. If a Timer 0 interrupt results from a Timer/Event Counter 0 overflow, and the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Location 010H
This area is reserved for program initialisation. After a device reset, the program always begins execution at location 000H.
* Location 004H
This location is reserved for the external RC oscillation converter interrupt service program. If an external RC oscillation converter interrupt results from an external RC oscillation converter interrupt is activated, and the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Location 014H
This location is reserved for the external interrupt 0 service program. If the INT0 input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Location 008H
This location is reserved for the Timer/Event Counter 1 interrupt service program. If a Timer 1 interrupt results from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Location 018H
This location is reserved for the external interrupt 1 service program. If the INT1 input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at this location.
000H 004H 008H 00CH D e v ic e In itia liz a tio n P r o g r a m E x te rn a l In te rru p t 0 E x te rn a l In te rru p t 1 T im e r /E v e n t C o u n te r 0 O v e r flo w
This location is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and if the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Table location
0 1 0 H E x te r n a l R C O s c illa tio n C o n v e r te r In te r r u p t 014H 018H T im e r /E v e n t C o u n te r 1 O v e r flo w A /D C o n v e rte r In te rru p t P ro g ra m M e m o ry
n00H nFFH F00H FFFH
L o o k - u p T a b le ( 2 5 6 w o r d s )
L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 5 - B its N o te : n ra n g e s fro m 0 to F
Program Memory
Any location in the program memory can be used as a look-up table. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 1 bit is read as 0. The table higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors may Table Location
Instruction TABRDC [m] TABRDL [m]
*11 P11 1
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits Rev. 1.00 8 December 13, 2006 P11~P8: Current program counter bits
HT45R38
therefore occur. In other words, using the table read instruction in the main routine and also in the ISR should be avoided. However, if the table read instruction has to be used in both the main routine and in the ISR, the interrupt should be disabled prior to the table read instruction execution. The interrupt should not be re-enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only. The stack is organised into 6-levels and is neither part of the data nor part of the program space, and is neither readable nor writable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the program counter is restored to its previous value from the stack. After a device reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost as only the most recent 6 return addresses are stored. Data Memory - RAM The data memory has a capacity of 2308 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (1928). Most are read/write, but some are read only. The special function registers include the Indirect addressing registers (00H, 02H), Timer/Event Counter 0 (TMR;0DH), Timer/Event Counter 0 control register (TMR0C;0EH), Timer/Event Counter 1 (TMR1;10H), Timer/Event Counter 1 control register (TMR1C;11H), Program counter lower-order byte register (PCL;06H), Memory pointer registers (MP0;01H, MP1;03H), Accumulator (ACC;05H), Table pointer (TBLP;07H), Table higher-order byte register (TBLH;08H), Watchdog Timer option setting register (WDTS;09H), Status register (STATUS;0AH), Interrupt control register 0 (INTC0; 0BH), Interrupt control register 1 (INTC1;1EH), Analog switch control register (ASCR;1CH), PWM data register (PWM0;1AH, PWM1;1BH), the Timer/Event Counter A higher-order byte register (TMRAH;20H), the Timer/Event Counter A lower-order byte register
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 3FH 40H FFH ADRL ADRH ADCR ACSR TM RAH TM RAL RCOCCR TM RBH TM RBL RCOCR OPAC IN T C 1 TM R1 TM R1C PA PAC PB PBC PC PCC PE PEC PW M0 PW M1 ASCR S p e c ia l P u r p o s e D a ta M e m o ry TM R0 TM R0C ACC PCL TBLP TBLH W DTS STATUS IN T C 0 In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1
G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s )
:U nused, re a d a s "0 0 "
RAM Mapping (TMRAL;21H), the RC oscillation converter control register (RCOCCR;22H), the Timer/Event Counter B higher-order byte register (TMRBH;23H), the Timer/Event Counter B lower-order byte register (TMRBL;24H), and the RC oscillator control register (RCOCR;25H), the A/D result lower-order byte register (ADRL;28H), the A/D result higher-order byte register (ADRH;29H), the A/D control register (ADCR;2AH), the 9 December 13, 2006
Rev. 1.00
HT45R38
A/D clock setting register (ACSR;2BH), the Operation Amplifier control register (OPAC;26H), I/O registers (PA;12H, PB;14H, PC;16H, PE;18H) and I/O control registers (PAC;13H, PBC;15H, PCC;17H, PEC;19H). The general purpose data memory, addressed from 40H to FFH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i bit manipulation instructions. They are also indirectly accessible through the memory pointer registers (MP0;01H, MP1;02H). Indirect Addressing Register The method of indirect addressing allows data manipulation using memory pointers instead of the usual direct memory addressing method where the actual memory address is defined. Any action on the indirect addressing registers will result in corresponding read/write operations to the memory location specified by the corresponding memory pointers. This device contains two indirect addressing registers known as IAR0 and IAR1 and two memory pointers MP0 and MP1. Note that these indirect addressing registers are not physically implemented and that reading the indirect addressing registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation. The two memory pointers, MP0 and MP1, are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related memory pointer. Direct data transfer between two indirect addressing Bit No. 0 Label C registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the Program Memory by combining corresponding indirect addressing registers. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected only by a system power-up, a WDT time-out or executing the CLR WDT or HALT instruction.
Function C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
Rev. 1.00
10
December 13, 2006
HT45R38
The PDF flag can be affected only by executing a HALT or CLR WDT instruction or a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The devices provides two external interrupts, two internal 8-bit timer/event counter interrupt, one external RC oscillation converter interrupt and the A/D converter interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable and interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, by clearing the EMI bit. This scheme may prevent further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 and INTC1 registers may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at a specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the accumulator or status register are altered by the interrupt service program, this may corrupt the desired control sequence, therefore their contents should be saved in advance. External interrupts are triggered by an edge transition on pins INT0 or INT1. A configuration option enables these pins as interrupts and selects if they are active on high to low or low to high transitions. If active their related interrupt request flag, EIF0; bit 4 in INTC0, and EIF1; bit 5 in INTC0, will be set. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H will occur. The interrupt request flags, EIF0 or EIF1, and the EMI bit will all be cleared to disable other interrupts. The internal Timer/Event Counter 0 interrupt is initialised by setting the Timer/Event Counter 0 interrupt request flag,T0F; bit 6 in INTC0. A timer interrupt will be generated when the timer overflows. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag, T0F, is reset, and the EMI bit is cleared to disable other interrupts. The internal Timer/Event Counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (T1F; bit 5 of INTC1), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T1F bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (T1F) is reset, and the EMI bit is cleared to disable other interrupts. The external RC Oscillation Converter interrupt is initialized by setting the external RC Oscillation Converter interrupt request flag, RCOCF; bit 4 of INTC1. This is caused by a Timer A or Timer B overflow. When the interrupt is enabled, and the stack is not full and the RCOCF bit is set, a subroutine call to location 10H will occur. The related interrupt request flag, RCOCF , will be reset and the EMI bit cleared to disable further interrupts. The A/D converter interrupt is initialised by setting the A/D converter request flag (ADF; bit 6 of the INTC1), caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF is set, a subroutine call to location 18H will occur. The related interrupt request flag (ADF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1, if the stack is not full. To return from the interrupt subroutine, a RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External Interrupt 0 External Interrupt 1 Timer/Event Counter 0 Overflow External RC Oscillation Converter Interrupt Timer/Event Counter 1 Overflow A/D Converter Interrupt Interrupt Priority Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H
Rev. 1.00
11
December 13, 2006
HT45R38
Bit No. 0 1 2 3 4 5 6 7 Label EMI EEI0 EEI1 ET0I EIF0 EIF1 T0F 3/4 Function Controls the master (global) interrupt (1= enabled; 0= disabled) Controls the external interrupt 0 (1= enabled; 0= disabled) Controls the external interrupt 1 (1= enabled; 0= disabled) Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled) External interrupt 0 request flag (1= active; 0= inactive) External interrupt 1 request flag (1= active; 0= inactive) Internal Timer/Event Counter 0 request flag (1= active; 0= inactive) Unused bit, read as 0 INTC0 (0BH) Register Bit No. 0 1 2 3, 7 4 5 6 Label ET1I EADI 3/4 T1F ADF Function Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled) Control the A/D converter interrupt (1= enabled; 0= disabled) Unused bit, read as 0 Internal Timer/Event Counter 1 request flag (1= active; 0= inactive) A/D converter request flag (1= active; 0= inactive) INTC1 (1EH) Register The Timer/Event Counter 0 interrupt request flag, T0F, external interrupt 1 request flag, EIF1, external interrupt 0 request flag, EIF0, enable Timer/Event Counter 0 interrupt bit, ET0I, enable external interrupt 1 bit, EEI1, enable external interrupt 0 bit, EEI0, and enable master interrupt bit, EMI, form the interrupt control register 0, INTC0, which is located at 0BH in the RAM. The Timer/Event Counter 1 interrupt request flag (T1F), external RC Oscillation Converter interrupt request flag (RCOCF), A/D converter request flag (ADF), enable Timer/Event Counter 1 interrupt bit (ET1I), enable external RC Oscillation Converter interrupt bit (ERCOCI) and enable A/D converter interrupt bit (EADI), form the interrupt control register 1 (INTC1) which is located at 1EH in the RAM. EMI, EEI0, EEI1, ET0I, ET1I, ERCOCI and EADI, are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags, EIF0, EIF1, T0F, T1F, RCOCF and ADF, are all set, they remain in the INTC1 or INTC0 registers respectively until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence may be damaged once the CALL is executed in the interrupt subroutine. Oscillator Configuration There are two oscillator circuits in the microcontroller.
V
DD
ERCOCI Controls the external RC oscillation converter interrupt (1= enabled; 0= disabled)
RCOCF External RC oscillation converter request flag (1= active; 0= inactive)
OSC1
470pF fS Y S /4 N M O S O p e n D r a in
OSC1
OSC2 C r y s ta l O s c illa to r
OSC2 R C O s c illa to r
System Oscillator Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, the choice of which is determined by a configuration option. When the device enters the Power Down Mode, the system oscillator will stop running and will ignore external signals to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VDD is required to produce oscillation. The resistance must range from 24kW to 1MW. The system clock, divided by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution, however, the frequency of oscillation may vary with VDD, temperatures and the device itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired.
Rev. 1.00
12
December 13, 2006
HT45R38
If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors connected between OSC1, OSC2 and ground are required, if the oscillator frequency is less than 1MHz. The WDT oscillator is a free running on-chip RC oscillator which requires no external components. Even if the system enters the Power Down Mode, where the system clock is stopped, the WDT oscillator will continue to operate with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by a configuration option to conserve power. Watchdog Timer - WDT The WDT clock can be sourced from its own dedicated internal oscillator (WDT oscillator), or from the or instruction clock, which is the system clock divided by 4. The choice is determined via a configuration option. The WDT timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by a configuration option. If the Watchdog Timer is disabled, any executions related to the WDT result in no operation. The WDT clock source is first divided by 256. If the internal WDT oscillator is used ,this gives a nominal time-out period of approximately 17ms at 5V. This time-out period may vary with temperatures, VDD and process variations. By using the WDT prescaler, longer time-out periods can be realised. Writing data to the WS2, WS1, WS0 bits in the WDTS register, can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio will be 1:128, and the maximum time-out period will be 2.1s at 5V. If the internal WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the Power Down state the WDT will stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. The high nibble and bit 3 of the WDTS can be used for user defined flags. If the device operates in a noisy environment, using the internal WDT oscillator is the recommended choice, since the HALT instruction will stop the system clock. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
WDTS (09H) Register The WDT overflow under normal operation will generate a chip reset and set the status bit TO. But in the Power Down mode, the overflow will generate a warm reset, where only the Program Counter and SP are reset to zero. To clear the contents of the WDT, including the WDT prescaler, three methods can be used; an external reset (a low level to RES), a software instruction and a HALT instruction. The software instruction includes CLR WDT instruction and the instruction pair CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the configuration option - CLR WDT times selection op tion. If the CLR WDT is selected, i.e. CLRWDT times equal one, any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen, i.e. CLRWDT times equal two, these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of a time-out. Power Down Operation - HALT The Power Down mode is initialized by the HALT instruction and results in the following...
* The system oscillator will be turned off but the WDT
oscillator keeps running, if the internal WDT oscillator has been selected as the WDT source clock. * The contents of the on chip RAM and registers remain unchanged.
* The WDT and WDT prescaler will be cleared and will
resume counting, if the internal WDT oscillator has been selected as the WDT source clock * All of the I/O ports will maintain their original status.
* The PDF flag is set and the TO flag is cleared.
The system can leave the Power Down Mode by means of an external reset, an interrupt, an external falling
W D T P r e s c a le r
S y s te m
C lo c k /4 W DT OSC O p tio n S e le c t
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
Rev. 1.00
13
December 13, 2006
HT45R38
edge signal on port A or a WDT overflow. An external reset causes a device initialisation and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the reason for chip reset can be determined. The PDF flag is cleared by a system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the program counter and SP; the other registers maintain their their original status. The port A and interrupt methods of wake-up can be considered as a continuation of normal execution. Each bit in port A can be independently selected by configuration options to wake-up the device. When awakened from an I/O port stimulus, the program will resume execution at the next instruction. If it is awakened due to an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power Down mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock periods) to resume normal operation. In other words, a dummy period will be inserted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimise power consumption, all the I/O pins should be carefully managed before entering the Power Down Mode. Reset There are three ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
VDD RES S S T T im e - o u t C h ip R eset tS
ST
that it can perform a warm reset that resets only the Program Counter and the SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to their initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between the different device reset types. TO PDF 0 u 0 1 1 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
Note: u means unchanged To guarantee that the system oscillator is started and stabilised, the SST or System Start-up Timer, provides an extra-delay of 1024 system clock pulses when the system is reset (power-up, WDT time-out or RES reset) or when the system awakens from a Power Down state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. An extra option load time delay is added during a system reset (power-up, WDT time-out at normal mode or RES reset). The functional unit device reset status are shown below. Program Counter Interrupt Prescaler WDT 000H Disable Clear Clear. After master reset, WDT begins counting Input mode Points to the top of the stack
Timer/Event Counter Off Input/Output Ports Stack Pointer
A WDT time-out, when the device is in the Power Down mode, is different from other device reset conditions, in
V
DD
Reset Timing Chart
0 .0 1 m F *
100kW RES 10kW 0 .1 m F *
HALT W DT
RES
W a rm
R eset
Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.00 14
OSC1
SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Reset Configuration December 13, 2006
HT45R38
The states of the registers is summarized in the table. Register MP0 MP1 ACC Program Counter TBLP TBLH WDTS STATUS INTC0 TMR0 TMR0C TMR1 TMR1C PA PAC PB PBC PC PCC PE PEC PWM0 PWM1 ASCR INTC1 TMRAH TMRAL RCOCCR TMRBH TMRBL RCOCR OPAC ADRL ADRH ADCR ACSR Reset (Power-on) xxxx xxxx xxxx xxxx xxxx xxxx 000H xxxx xxxx -xxx xxxx 0000 0111 --00 xxxx -000 0000 xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 xxxx xxxx xxxx xxxx ---1 1111 -000 -000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 xxxx xxxx xxxx ---xxxx xxxx 0100 0000 ---- --00 WDT Time-out (Normal Operation) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --1u uuuu -000 0000 xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 xxxx xxxx xxxx xxxx ---1 1111 -000 -000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 xxxx xxxx xxxx ---xxxx xxxx 0100 0000 ---- --00 RES Reset (Normal Operation) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --uu uuuu -000 0000 xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 xxxx xxxx xxxx xxxx ---1 1111 -000 -000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 xxxx xxxx xxxx ---xxxx xxxx 0100 0000 ---- --00 RES Reset (HALT) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --01 uuuu -000 0000 xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 xxxx xxxx xxxx xxxx ---1 1111 -000 -000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 xxxx xxxx xxxx ---xxxx xxxx 0100 0000 ---- --00 WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu ---u uuuu uuuu uuuu uuuu uuuu ---u uuuu -uuu -uuu uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu ---uuuu uuuu uuuu uuuu ---- --uu
Note: * means warm reset u means unchanged x means unknown Rev. 1.00 15 December 13, 2006
HT45R38
Timer/Event Counter 0/1 Two timer/event counters are implemented in the microcontroller. Timer/Event Counter 0 is an 8-bit programmable count-up counter whose clock may come from an external source or from an internal clock source. This internal clock source is the system clock. Timer/Event Counter 1 is also an 8-bit programmable count-up counter whose clock may come from an external source or from an internal clock source. This internal clock source is the system clock/4. Using an external clock input allows the user to count external events, measure time intervals or pulse widths. Using the internal clock allows an accurate time base to be generated. There are two registers related to Timer/Event Counter 0; TMR0 (0DH), TMR0C (0EH), and two registers related to Timer/Event Counter 1; TMR1(10H), TMR1C (11H). Writing to either Timer/Event Counter places a start value in the Timer/Event Counter 0/1 preload register while reading the Timer/Event Counter retrieves the contents of the Timer/Event Counter 0/1. The TMR0C and TMR1C registers are the Timer/Event Counter control register 0/1, which define the operating mode, the count enable or disable and the active edge type. The T0M0/T1M0 and T0M1/T1M1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source will come from the external timer pin, TMR0 or TMR1. The timer mode functions as a normal timer with the clock source coming from the internal system clock. The pulse width measurement mode can be used to measure the duration of a high or low level external signal on pin TMR0 or TMR1. The counting will be based on the internally selected clock source. In the event count or timer mode, the timer/event counter 0/1 starts counting at the current contents in the timer/event counter and ends at FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag, which is the T0F; bit 6 of INTC0, or the T1F; bit 5 of INTC1. In the pulse width measurement mode with the values of the T0ON/T1ON and T0E/T1E bits equal to 1, after the TMR0 or TMR1 pin has received a low to high transient, or high to low if the T0E/T1E bit is 0, it will start counting until the TMR0 or TMR1 pin returns to its original level at which point it will reset the T0ON/T1ON bit. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only a single shot measurement can be made. Not until the T0ON/T1ON bit is set again, by the program, can another measurement be made. In this operation mode, the timer/event counter begins counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event counter and timer modes. To enable the counting operation, the Timer ON bit, T0ON; bit 4 of the TMR0C register or T1ON; bit 4 of the TMR1C register, should be set to 1. In the pulse width measurement mode, the T0ON/T1ON bit is automatically cleared after the measurement cycle is completed. But in the other two modes, the T0ON/T1ON bit can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt servicing.
D a ta B u s
T
fS
YS
7 - S ta g e P r e s c a le r 8 -1 M U X T0PSC 2~T0PSC 0 TM R0 T0E T0M 1 T0M 0 T0O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - B it T im e r /E v e n t C o u n te r (T M R 0 ) O v e r flo w to In te rru p t f IN T0M 1 T0M 0
8 - B it T im e r /E v e n t C o u n te r R e lo a d P r e lo a d R e g is te r
Timer/Event Counter 0
fS Y S /4 T1M 1 T1M 0 T1E T1M 1 T1M 0 T1O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - b it T im e r /E v e n t C o u n te r (T M R 1 ) O v e r flo w to In te rru p t D a ta B u s 8 - b it T im e r /E v e n t C o u n te r R e lo a d P r e lo a d R e g is te r
TM R1
Timer/Event Counter 1
Rev. 1.00
16
December 13, 2006
HT45R38
If the timer/event counter is not running, writing data to the timer/event counter preload register also reloads that data into the timer/event counter. But if the timer/event counter is already running, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter will continue running until an overflow occurs and only then will the data be loaded into the timer/event counter. Bit No. Label When the timer/event counter is read, the clock is blocked to avoid errors, and as this may results in a counting error, it should be taken into account by the programmer. Bit0~bit2 of the TMR0C register can be used to define the timer/event counter clock division ratio. The definitions are as shown. Function
0~2
To define the prescaler stages, T0PSC2, T0PSC1, T0PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 T0PSC0~T0PSC2 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 To define the TMR0 active edge of the timer/event counter In event counter mode (T0M1, T0M0)= (0, 1) 0: count on rising edge; 1: count on falling edge In pulse width measurement mode (T0M1, T0M0)= (1, 1) 0: start counting on the falling edge, stop on the rising edge; 1: start counting on the rising edge, stop on the falling edge To enable or disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 To define the operating mode, T0M1, T0M0= 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH) Register
3
T0E
4 5
T0ON 3/4
6 7
T0M0 T0M1
Bit No. 0~2, 5
Label 3/4 Unused bit, read as 0
Function
3
T1E
To define the TMR0 active edge of the timer/event counter In event counter mode (T1M1, T1M0)= (0, 1) 0: count on rising edge; 1: count on falling edge In pulse width measurement mode (T1M1, T1M0)= (1, 1) 0: start counting on the falling edge, stop on the rising edge; 1: start counting on the rising edge, stop on the falling edge To enable or disable timer counting (0=disabled; 1=enabled) To define the operating mode, T0M1, T0M0= 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register
4
T1ON
6 7
T1M0 T1M1
Rev. 1.00
17
December 13, 2006
HT45R38
External RC Oscillation Converter An external RC oscillation mode is implemented in the device. The RC oscillation converter contains two 16-bit programmable count-up counters and the Timer A clock source may come from the system clock or system clock/4. The timer B clock source may come from the external RC oscillator. The RC oscillation converter is comprised of the TMRAL, TMRAH, TMRBL, TMRBH registers when the RCO bit, bit 1 of RCOCR register, is 1. The RC oscillation converter Timer B clock source may come from an external RC oscillator. The Timer A clock source comes from the system clock or from the system clock/4, determined by the RCOCCR register. Bit No. 0~2 3 4 Label 3/4 3/4 Unused bit, read as 0 Undefined bit, this bit can read/write There are six registers related to the RC oscillation converter, i.e., TMRAH, TMRAL, RCOCCR, TMRBH, TMRBL and RCOCR. The internal timer clock is the input to TMRAH and TMRAL, the external RC oscillation is the input to TMRBH and TMRBL. The OVB bit, bit 0 of RCOCR register, decides whether Timer A overflows or Timer B overflows, then the RCOCF bit is set and an external RC oscillation converter interrupt occurs. When the RC oscillation converter mode Timer A or Timer B overflows, the RCOCON bit is reset to 0 and stops counting. Writing to TMRAH/TMRBH places the start value in Timer A/Timer B while reading TMRAH/TMRBH obtains the contents of Timer A/Timer B. Writing to TMRAL/TMRBL only writes the data into a low byte buffer. However writing to TMRAH/TMRBH will write the Function
RCOCON To enable or disable external RC oscillation converter counting (0= disabled; 1= enabled) To define the Timer A clock source, RCOM2, RCOM1, RCOM0= 000= System clock 001= System clock/4 RCOM0 010= Unused RCOM1 011= Unused RCOM2 100= Unused 101= Unused 110= Unused 111= Unused RCOCCR (22H) Register
5 6 7
Bit No. 0
Label OVB
Function In the RC oscillation converter mode, this bit is used to define the timer/event counter interrupt, which comes from Timer A overflow or Timer B overflow. (0= Timer A overflow; 1= Timer B overflow) Define 16 timer/event counter mode or RC oscillation converter mode. (0= Disable RC oscillation converter mode; 1= Enable RC oscillation converter mode) Unused bit, read as 0 4-bit read/write registers for user defined. RCOCR (25H) Register
S1 S2 O VB=0 T im e r A RCOCON O VB=1 T im e r B RC OSC O u tp u t R esetR C O C O N E x te rn a l R C O s c illa tio n C o n v e r te r In te r r u p t
1 2~3 4~7
RCO 3/4 RW
S y s te m S y s te m
C lo c k C lo c k /4
External RC Oscillation Converter
Rev. 1.00
18
December 13, 2006
HT45R38
data and the contents of the low byte buffer into the Timer A/Timer B (16-bit) simultaneously. Timer A/Timer B is changed by writing to TMRAH/TMRBH but writing to TMRAL/TMRBL will keep the Timer A/Timer B unchanged. R e a d in g TM R A H / TM R B H w i l l al s o l at ch t h e TMRAL/TMRBL into the low byte buffer to avoid the false timing problem. Reading TMRAL/TMRBL returns the contents of the low byte buffer. In other word, the low byte of Timer A/Timer B can not be read directly. It must read the TMRAH/TMRBH first to ensure that the low byte contents of Timer A/Timer B are latched into the buffer. The resistor and capacitor form an oscillation circuit and input to TMRBH and TMRBL. The RCOM0, RCOM1 and RCOM2 bits of RCOCCR define the clock source of Timer A. It is recommended that the clock source of Timer A uses the system clock or the instruction clock. If the RCOCON bit, bit 4 of RCOCCR, is set to 1, Timer A and Timer B will start counting until Timer A or Timer B overflows, the timer/event counter will then generate an interrupt request flag which is RCOCF; bit 4 of INTC1. The Timer A and Timer B will stop counting and will reset the RCOCON bit to 0 at the same time. If the RCOCON bit is 1, TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written.
External RC oscillation converter mode example program - Timer A overflow: clr RCOCCR mov a, 00000010b ; Enable External RC oscillation mode and set Timer A overflow mov RCOCR,a clr intc1.4 ; Clear External RC Oscillation Converter interrupt request flag mov a, low (65536-1000) ; Give timer A initial value mov tmral, a ; Timer A count 1000 time and then overflow mov a, high (65536-1000) mov tmrah, a mov a, 00h ; Give timer B initial value mov tmrbl, a mov a, 00h mov tmrbh, a mov a, 00110000b ; Timer A clock source=fSYS/4 and timer on mov RCOCCR, a p10: clr wdt snz intc1.4 ; Polling External RC Oscillation Converter interrupt request flag jmp p10 clr intc1.4 ; Clear External RC Oscillation Converter interrupt request flag ; Program continue
Rev. 1.00
19
December 13, 2006
HT45R38
Analog Switch There are 12 analog switch lines in the microcontroller for RC1~RC12, and a corresponding Analog Switch control register, which is mapped to the data memory of 1CH. Bit No. Label Function Defines the analog switch for RC1~RC12 which is on. ASON= 00000b= Analog switch 1 on, other analog switch off 00001b= Analog switch 2 on, other analog switch off 00010b= Analog switch 3 on, other analog switch off 00011b= Analog switch 4 on, other analog switch off 00100b= Analog switch 5 on, other analog switch off 00101b= Analog switch 6 on, other analog switch off 00110b= Analog switch 7 on, other analog switch off 00111b= Analog switch 8 on, other analog switch off 01000b= Analog switch 9 on, other analog switch off 01001b= Analog switch 10 on, other analog switch off 01010b= Analog switch 11 on, other analog switch off 01011b= Analog switch 12 on, other analog switch off 01100b= All analog switch off 01101b= All analog switch off 01110b= All analog switch off 01111b= All analog switch off 1xxxxb= All analog switch off and RC OSC always off Unused bit, read as 0 ASCR (1CH) Register
0~4
ASON
5~7
3/4
ASON
RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 RC10 RC11 RC12 RCOUT
IN RREF
T .G .1 T .G .2 T .G .3 T .G .4 T .G .5 T .G .6 T .G .7 T .G .8 T .G .9
T .G .1 0 T .G .1 1 T .G .1 2
CREF
T im e r B
Analog Switch
Rev. 1.00
20
December 13, 2006
HT45R38
Input/Output Ports There are 29 bidirectional input/output lines in the microcontroller, labeled as PA, PB, PC and PE, which are mapped to the data memory at [12H], [14H], [16H] and [18H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register, known as PAC, PBC, PCC and PEC, to control the input/output configuration. With this control register, a CMOS output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically, i.e. on-the-fly, under software control. To function as an input, the corresponding latch of the control register must written with a 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For an output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H and 19H. After a chip reset, the port control registers will default to a high state, which is an input condition. They may be floating or be pulled high if pull-high resistors are connected. Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H, 16H or 18H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. The highest bits, 5,6 and 7, of port E are not physically implemented; on reading them a 0 is returned whereas writing to them results in no operation. Each I/O line has a pull-high configuration option. It should be noted that an input line without a connected pull-high resistor will be in a floating state. PA0, PA1, PA3, PA4, PA5 and PA6 are pin-shared with PWM0, PWM1, INT0, INT1, TMR0 and TMR1 pins, respectively. The PE port can also be used as A/D converter inputs. The A/D function will be described later. The PWM outputs are shared with pins PA0/PA1. If the PWM function is enabled, the PWM0/PWM1 signals will appear on PA0/PA1. Note that PA0/PA1 must be setup as outputs for the PWM output to function. The I/O functions of PA0/PA1 are as shown. I/O Mode PA0 PA1 I/P O/P (Normal) (Normal) Logical Input Logical Output I/P (PWM) Logical Input O/P (PWM) PWM0 PWM1
It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state.
V
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
C o n tr o l B it P u ll- h ig h Q D CK S Q
D a ta B it Q D CK S Q M U X
W r ite D a ta R e g is te r
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PC0 PE0
/P W M 0 /P W M 1 /IN /IN /T /T T1 MR0 MR1 T0
~PB7 ~PC7 /A N 0 ~ P E 4 /A N 4
P A 0 /P A 1 P W M 0 /P W M 1 M R e a d D a ta R e g is te r
S y s te m W a k e - u p ( P A o n ly )
U X
EN
(P W M x )
O P0~O P7
IN IN TM TM
T0 T0 R0 R1
fo fo fo fo
rP rP rP rP
A3 A4 A5 A6
On On On On
ly ly ly ly
Input/Output Ports
Rev. 1.00
21
December 13, 2006
HT45R38
Pulse Width Modulator Each device contains a dual channel internal PWM function. Useful for such applications such as motor speed control, the PWM function provides outputs with a fixed frequency but with a duty cycle that can be varied by placing particular values into the corresponding PWM register. A single register, located in the Data Memory is assigned to each of the two PWM outputs. These registers assume the names PWM0 and PWM1. It is here that the 8-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. To increase the PWM modulation frequency, each modulation cycle is modulated into two or four individual modulation sub-sections, known as the 7+1 mode or 6+2 mode respectively. Each device can choose which mode to use by selecting the appropriate configuration option. When a mode configuration option is chosen, it applies to both of the PWM outputs on the device. Note that when using the PWM it is only necessary to write the required value into the appropriate PWM register and select the required mode configuration option, the subdivision of the waveform into its sub-modulation cycles is done automatically within the microcontroller hardware. The PWM clock source is the system clock fSYS. PWM Mode 6+2 or 7+1 6+2 or 7+1 Output Pin PA0 PA1 PWM Function Table This method of dividing the original modulation cycle into a further 2 or 4 sub-cycles enables the generation of higher PWM frequencies, which allow a wider range of applications to be served. As long as the periods of the generated PWM pulses are less than the time constants of the load, the PWM output will be suitable as such long PWM Register Name PWM0 PWM1 Parameter AC (0~3) i* 6+2 PWM Mode
PWM Cycle PWM Cycle Frequency Duty fSYS/256 [PWM]/256
Each full PWM cycle, as it is controlled by an 8-bit PWM register, has 256 clock periods. However, in the 6+2 PWM Mode, each PWM cycle is subdivided into four individual sub-cycles known as modulation cycle 0 ~ modulation cycle 3, denoted as i in the table. Each one of these four sub-cycles contains 64 clock cycles. In this mode, a modulation frequency increase by a factor of four is achieved. The 8-bit PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit2~bit7 is denoted here as the DC value. The second group which consists of bit0~bit1 is known as the AC value. In the 6+2 PWM mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table. DC (Duty Cycle) DC 1 64 DC 64
6+2 Mode Modulation Cycle Values
Rev. 1.00
22
December 13, 2006
HT45R38
The following diagram illustrates the waveforms associated with the 6+2 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into 4 individual modulation cycles, numbered from 0~3 and how the AC value is related to the PWM value.
fS
YS
/2
[P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0
YS
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4 M o d u la tio n c y c le 1 PW M
2 6 /6 4 M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS
YS
2 5 /6 4 M o d u la tio n c y c le 3
2 6 /6 4 M o d u la tio n c y c le 0
6+2 PWM Mode
b7 b0 PW M AC R e g is te r v a lu e (6 + 2 ) M o d e
D C v a lu e
PWM Register for 6+2 Mode
* 7+1 PWM Mode
Each full PWM cycle, as it is controlled by an 8-bit PWM register has 256 clock periods. However, in the 7+1 PWM mode, each PWM cycle is subdivided into two individual sub-cycles, known as modulation cycle 0 and modulation cycle 1, denoted as i in the table. Each one of these two sub-cycles contains 128 clock cycles. In this mode, a modulation frequency increase by a factor of two is achieved. The 8-bit PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit1~bit7 is denoted here as
the DC value. The second group which consists of bit0 is known as the AC value. In the 7+1 PWM mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. Parameter AC (0~1) iModulation cycle i (i=0~1)
7+1 Mode Modulation Cycle Values
Rev. 1.00
23
December 13, 2006
HT45R38
The following diagram illustrates the waveforms associated with the 7+1 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into 2 individual modulation cycles, numbered 0 and 1 and how the AC value is related to the PWM value.
fS
YS
/2
[P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M 5 2 /1 2 8 PW M m o d u la tio n p e r io d : 1 2 8 /fS M o d u la tio n c y c le 0 PW M c y c le : 2 5 6 /fS
YS YS
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
M o d u la tio n c y c le 1
M o d u la tio n c y c le 0
7+1 PWM Mode
b7 b0 PW M AC DC R e g is te r v a lu e v a lu e (7 + 1 ) M o d e
PWM Register for 7+1 Mode
* PWM Output Control
The PWM outputs are pin-shared with the Port A I/O pins. To operate as PWM outputs and not as I/O pins, the correct PWM configuration options must be selected. A 0 must also be written to the corresponding bits in the I/O port control register PAC to ensure that the required PWM output pins are setup as outputs. After these two initial steps have been carried out, and of course after the required PWM value has been written into the PWM register, writing a 1 to the corresponding bit in the PA output data register will enable clr PAC.0 clr PAC.1 set pa.0 mov a,64h mov pwm0,a set pa.1 mov a,65h mov pwm1,a clr pa.0 clr pa.1 Rev. 1.00 ; set pin PA0 as output ; set pin PA1 as output
the PWM data to appear on the pin. Writing a 0 to the corresponding bit in the PA output data register will disable the PWM output function and force the output low. In this way, the Port A data output register can be used as an on/off control for the PWM function. Note that if the configuration options have selected the PWM function, but a 1 has been written to its corresponding bit in the PAC control register to configure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor configuration options.
; PA.0=1; enable pin PA0/PWM0 to be the PWM channel 0 ; PWM0=100D=64H
; PA.1=1; enable pin PA1/PWM1 to be the PWM channel 1 ; PWM1=101D=65H
; disable PWM0 output - PA.0 will remain low ; disable PWM1 output - PA.1 will remain low 24 December 13, 2006
HT45R38
A/D Converter The 5 channels 12-bit resolution A/D converter are implemented in this microcontroller. The A/D converter contains 4 special registers which are; ADRL (28H), ADRH (29H), ADCR (2AH) and ACSR (2BH). The ADRH and ADRL are A/D result register higher-order byte and lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If the users want to start an A/D conversion, define PE configuration, select the converted analog channel, and give START bit a raising edge and falling edge (0(R)1(R)0). At the end of A/D conversion, the EOCB bit is cleared and an A/D converter interrupt occurs (if the A/D converter interrupt is enabled). The ACSR is A/D clock setting register, which is used to select the A/D clock source. The A/D converter control register is used to control the A/D converter. The bit2~bit0 of the are used to select an analog input channel. There are a total of five channels to select. The bit5~bit3 of the ADCR are used to set PE configurations. PE can be an analog input or as digital I/O line determined by these 3 bits. Once a PE line is seBit No. Label Selects the A/D converter clock source 00= system clock/2 01= system clock/8 10= system clock/32 11= undefined Unused bit, read as 0 ACSR (2BH) Register Bit No. 0 1 2 3 4 5 Label ACS0 ACS1 ACS2 PCR0 PCR1 PCR2 Defines the analog channel select Function lected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled and the A/D converter circuit is powered on. The EOCB bit (bit6 of the ADCR) is end of A/D conversion flag. Check this bit to know when the A/D conversion is completed. The START bit of the ADCR is used to begin the conversion of the A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In order to ensure that the A/D conversion is completed, the START should remain at 0 until the EOCB is cleared to 0 (end of A/D conversion). Bit1 and bit0 of the ACSR register are used to select the A/D clock source. When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to 1 when the START bit is set from 0 to 1. Important Note for A/D initialisation: Special care must be taken to initialise the A/D converter each time the Port E A/D channel selection bits are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialisation is implemented by setting the START bit high and then clearing it to zero within 10 instruction cycles of the Port E channel selection bits being modified. Note that if the Port E channel selection bits are all cleared to zero then an A/D initialisation is not required. Function
0 1
ADCS0 ADCS1
2~7
3/4
Defines the port E configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is powered off to reduce power consumption Indicates end of A/D conversion. (0= end of A/D conversion) Each time bits 3~5 change state the A/D should be initialised by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See Important note for A/D initialisation. Starts the A/D conversion. 0(R)1(R)0= Start 0(R)1= Reset A/D converter and set EOCB to 1. ADCR (2AH) Register
6
EOCB
7
START
Rev. 1.00
25
December 13, 2006
HT45R38
ACS2 0 0 0 0 1 1 1 1 ACS1 0 0 1 1 0 0 1 1 ACS0 0 1 0 1 0 1 0 1 Analog Channel AN0 AN1 AN2 AN3 AN4 * * *
Analog Input Channel Selection Note: * undefined, cannot be used Register ADRL (20H) ADRH (21H) Bit7 D3 D11 Bit6 D2 D10 Bit5 D1 D9 Bit4 D0 D8 Bit3 0 D7 Bit2 0 D6 Bit1 0 D5 Bit0 0 D4
Note: D0~D11 is A/D conversion result data bit LSB~MSB. PCR2 0 0 0 0 1 1 1 1 PCR1 0 0 1 1 0 0 1 1 PCR0 0 1 0 1 0 1 0 Undefined, cannot be used 1 Port E Configuration
M in im u m START o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d
4 PE4 PE4 PE4 PE4 PE4 AN4
3 PE3 PE3 PE3 PE3 AN3 AN3
2 PE2 PE2 PE2 AN2 AN2 AN2
1 PE1 PE1 AN1 AN1 AN1 AN1
0 PE0 AN0 AN0 AN0 AN0 AN0
EOCB PC R2~ PCR0
A /D tA 000B
DCS
s a m p lin g tim e 100B
A /D tA
DCS
s a m p lin g tim e
A /D tA
DCS
s a m p lin g tim e 000B 1 . P E p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n
100B
101B
AC S2~ ACS0
000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P E c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D N o te : A /D c lo c k m u s t b e fS tA D C S = 3 2 tA D tA D C = 8 0 tA D
YS
010B S ta rt o f A /D c o n v e r s io n
000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
d o n 't c a r e
E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e
tA D C c o n v e r s io n tim e
YS
A /D
tA D C c o n v e r s io n tim e
A /D
/2 , fS
/8 o r fS
YS
/3 2
A/D Conversion Timing
Rev. 1.00
26
December 13, 2006
HT45R38
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using EOCB Polling Method to detect end of conversion clr mov mov mov mov EADI a,00000001B ACSR,a a,00100000B ADCR,a : : ; disable ADC interrupt ; setup the ACSR register to select fSYS/8 as the A/D clock ; setup ADCR register to configure Port PE0~PE3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port E channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles
: Start_conversion: clr START set START clr START Polling_EOC: sz EOCB jmp polling_EOC mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a : : jmp Start_conversion
; reset A/D ; start A/D ; poll the ADCR register EOCB bit to detect end of A/D conversion ; continue polling ; read conversion result high byte value from the ADRH register ; save result to user defined memory ; read conversion result low byte value from the ADRL register ; save result to user defined memory
; start next A/D conversion
Example: using Interrupt Method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov mov a,00100000B ADCR,a : ; setup ADCR register to configure Port PE0~PE3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port E channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START clr START clr ADF set EADI set EMI : : : ; ADC interrupt service routine ADC_ISR: mov acc_stack,a mov a,STATUS mov status_stack,a : : mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a clr START set START clr START : : Rev. 1.00
; reset A/D ; start A/D ; clear ADC interrupt request flag ; enable ADC interrupt ; enable global interrupt
; save ACC to user defined memory ; save STATUS to user defined memory
; read conversion result high byte value from the ADRH register ; save result to user defined register ; read conversion result low byte value from the ADRL register ; save result to user defined register ; reset A/D ; start A/D
27
December 13, 2006
HT45R38
EXIT_INT_ISR: mov a,status_stack mov STATUS,a mov a,acc_stack reti
; restore STATUS from user defined memory ; restore ACC from user defined memory
OP Amplifier The device contains an internal Operational Amplifier, which can be used for amplification purposes. The OPA can be disabled or enabled under software control and by the OPA configuration option. OPA Configuration Option OPAEN Register PCR2~PCR0 Register 000B 001B 010B 011B 100B 101B 000B 001B 010B 011B 100B 101B 000B 001B 010B 011B 100B 101B Function PE0/AN0/OPO is digital input pin, OPA is disabled.
0
PE0/AN0/OPO is ADC channel 0 input pin, OPA is disabled.
Enable PE0/AN0/OPO is OPA output pin, OPA is enabled.
1
PE0/AN0/OPO is OPA output pin and OPA output signal is input to ADC channel 0, OPA is enabled.
PE0/AN0/OPO is digital input/output pin, OPA is disabled.
Disable*
0, 1
PE0/AN0/OPO is ADC channel 0 input pin, OPA is disabled.
Note: * If the OPA configuration option is disabled, the OPAEN (bit 7 of OPAC) must not be set an unknown value will be read. Bit No. 0~3 4 5 6 7 Label Function
AOF0~AOF3 Operational amplifier input offset voltage cancellation control bits ARS AOFM OPAOP OPAEN Operational amplifier input offset voltage cancellation reference selection bit 1/0: select OPP/OPN as the reference input Input offset voltage cancellation mode and operational amplifier mode selection 1/0: input offset voltage cancellation mode/operational amplifier mode Operational amplifier output; positive logic. This bit is read only. Operational amplifier enable/disable (1/0)
OPAC Register (Operational Amplifier Control Register)
OPP OPN P E 0 /A N 0 /O P O
S1 S2 S3 AO F0~AO F3 OPAEN P E 0 /A N 0 ARS 0 0 1 1 AOFM 0 1 0 1 S1 ON OFF ON ON S2 ON ON OFF ON S3 OFF ON OFF ON
OPA Block Diagram
Rev. 1.00
28
December 13, 2006
HT45R38
The OPA allows its input voltage offset to be adjusted by using common mode inputs to calibrate the offset. The calibration steps are as following:
OPP OPN P E 0 /A N 0 /O P O S1 S2 S3 AO F0~AO F3 OPAEN P E 0 /A N 0
Note: Set AOFM=1 to offset cancellation mode - S3 is closed Set ARS to select which input pin is the reference voltage - S1 or S2 closed Adjust AOF0~AOF3 until the output status has changed. Set AOFM=0 to normalise the OPA mode
Low Voltage Reset - LVR The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as when changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
V 3 .0 V 2 .2 V
The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
5 .5 V
LVR
* The low voltage (0.9V~VLVR) has to remain in its origi-
nal state for longer than tLVR. If the low voltage state does not exceed tLVR, the LVR will ignore it and will not perform a reset function.
* The LVR uses an OR function with the external RES
0 .9 V
signal to perform a chip reset.
Note: V OPR is the voltage range for proper chip operation at 4MHz system clock.
V 5 .5 V
DD
V
LVR
LVR
D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before starting the normal operation. *2: Since low voltage has to be maintained its original state for longer than tLVR, therefore a tLVR delay enters the reset mode.
Rev. 1.00
29
December 13, 2006
HT45R38
Options The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper system functioning. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Function Wake up PA0~PA7 (bit option) Pull high PA0~PA7 (bit option) Pull high PE0~PE4 (bit option) Pull high PB0~PB7 (port option) None wake-up or wake-up None pull-high or pull-high None pull-high or pull-high None pull-high or pull-high Description
Pull high PC0~PC7 (port option) None pull-high or pull-high OPA function WDT clock source WDT CLRWDT LVR OSC INT0 trigger edge INT1 trigger edge PWM0 output PWM1 output PWM mode Enable or disable WDTOSC or fSYS/4 Enable or disable 1 or 2 instructions Enable or disable Xtal mode or RC mode Disable, rising edge, falling edge or double edge Disable, rising edge, falling edge or double edge Enable or disable Enable or disable 6+2 mode or 7+1 mode
Rev. 1.00
30
December 13, 2006
HT45R38
Application Circuits
R to F Application Circuit
V
DD
PB0~PB7 0 .0 1 m F * VDD RES
10kW
PC 0~PC 7 P A 0 /P W M P A 1 /P W M PA P A 3 /IN T P A 4 /IN T P A 5 /T M R P A 6 /T M R PA 1 7 R R
sensor sensor
LED
D is p la y
100kW 0 .1 m F
0 2 0 0 1 1
0 .1 m F * VSS
RC1 OSC C ir c u it S e e R ig h t S id e P E 0 /A N 0 /O P O OPN OPP OSC1 OSC2 RC2 R
1 2
RC12 RREF RCOUT IN CREF
sensor
12 *R
V
DD
R
OSC
470pF
*C
OSC1 fS
YS
R C S y s te m O s c illa to r 24kW /4
OSC2 OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r
C1
P E 1 /A N 1 ~ P E 4 /A N 4 C2 R1
H T45R 38
OSC2 OSC
C ir c u it
C to F Application Circuit 1
V
DD
PB0~PB7 0 .0 1 m F * VDD RES
10kW
PC 0~PC 7 P A 0 /P W M P A 1 /P W M PA P A 3 /IN T P A 4 /IN T P A 5 /T M R P A 6 /T M R PA 1 7 C C 0 2 0 0 1 1
LED
D is p la y
100kW 0 .1 m F
0 .1 m F * VSS
RC1 OSC C ir c u it S e e R ig h t S id e P E 0 /A N 0 /O P O OPN OPP OSC1 OSC2 RC12 CREF RCOUT IN RREF C RC2
sensor sensor
1 2
sensor
12 *C
V
DD
R
OSC
470pF
*R
OSC1 fS
YS
R C S y s te m O s c illa to r 24kW /4
OSC2 OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r
C1
P E 1 /A N 1 ~ P E 4 /A N 4 C2 R1
H T45R 38
OSC2 OSC
C ir c u it
Rev. 1.00
31
December 13, 2006
HT45R38
C to F Application Circuit 2
PB0~PB7 V
DD
0 .0 1 m F * 100kW 0 .1 m F
VDD RES
10kW
0 .1 m F * VSS
PC 0~PC 7 P A 0 /P W M 0 P A 1 /P W M 1 PA2 P A 3 /IN T 0 P A 4 /IN T 1 P A 5 /T M R 0 P A 6 /T M R 1 PA7 RC1 RC2 C C
LED
D is p la y
sensor sensor
1 2
OSC C ir c u it S e e R ig h t S id e P E 0 /A N 0 /O P O OPN OPP
OSC1 OSC2 RC12 RCOUT IN RREF CREF C
sensor
12
V
DD
R
*R
OSC
470pF C1
OSC1 fS
YS
R C S y s te m O s c illa to r 24kW /4
OSC2 OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r
*C
P E 1 /A N 1 ~ P E 4 /A N 4 C2 R1
H T45R 38
OSC2
O S C C ir c u it
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) Crystal or Resonator 4MHz Crystal 8MHz Crystal 4MHz Resonator 8MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal 2MHz Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator 400kHz Resonator C1, C2 10pF 10pF 10pF 10pF 10pF 25pF 25pF 35pF 68pF 300pF 300pF 300pF 300pF R1 12kW 4.3kW 10kW 4.7kW 12kW 10kW 15kW 15kW 15kW 12kW 12kW 12kW 12kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. The *R resistance and *C capacitance should be consideration for the frequency of RC OSC. Rsensor1~Rsensor12 are the resistance sensors. Csensor1~Csensor12 are the capacitance sensors. Rev. 1.00 32 December 13, 2006
HT45R38
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
Rev. 1.00
33
December 13, 2006
HT45R38
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter Power Down Mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
Note: x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.00
34
December 13, 2006
HT45R38
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
Rev. 1.00
35
December 13, 2006
HT45R38
AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr
Operation Affected flag(s)
TO 3/4 CLR [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.00
36
December 13, 2006
HT45R38
CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation Affected flag(s) TO 0 CLR WDT1 Description PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CLR WDT2 Description
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CPL [m] Description Operation Affected flag(s) TO 3/4
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Rev. 1.00
37
December 13, 2006
HT45R38
CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TO 3/4 DAA [m] Description
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TO 3/4 DEC [m] Description Operation Affected flag(s) TO 3/4 DECA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
Rev. 1.00
38
December 13, 2006
HT45R38
HALT Description Enter Power Down Mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0
Operation
Affected flag(s) TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
Rev. 1.00
39
December 13, 2006
HT45R38
MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
Rev. 1.00
40
December 13, 2006
HT45R38
RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation Affected flag(s) TO 3/4 RETI Description Operation Affected flag(s) TO 3/4 RL [m] Description Operation Affected flag(s) TO 3/4 RLA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
Rev. 1.00
41
December 13, 2006
HT45R38
RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TO 3/4 RR [m] Description Operation Affected flag(s) TO 3/4 RRA [m] Description Operation Affected flag(s) TO 3/4 RRC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rev. 1.00
42
December 13, 2006
HT45R38
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TO 3/4 SDZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.00
43
December 13, 2006
HT45R38
SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TO 3/4 SIZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TO 3/4 SNZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.00
44
December 13, 2006
HT45R38
SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
Rev. 1.00
45
December 13, 2006
HT45R38
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation Affected flag(s) TO 3/4 TABRDL [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Note that this instruction is not valid for HT48R07A-1/HT48C07 [m] ROM code (low byte) TBLH ROM code (high byte)
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.00
46
December 13, 2006
HT45R38
XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 1.00
47
December 13, 2006
HT45R38
Package Information
52-pin QFP (1414) Outline Dimensions
C D 39 27 G H
I 40 26 F A B E
52
14 K J 1 13
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 17.3 13.9 17.3 13.9 3/4 3/4 2.5 3/4 3/4 0.73 0.1 0 Nom. 3/4 3/4 3/4 3/4 1 0.4 3/4 3/4 0.1 3/4 3/4 3/4 Max. 17.5 14.1 17.5 14.1 3/4 3/4 3.1 3.4 3/4 1.03 0.2 7
Rev. 1.00
48
December 13, 2006
HT45R38
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holmate.com
Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
49
December 13, 2006

▲Up To Search▲

Price & Availability of HT45R38

	To Download HT45R38 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .